Siddhant Cocasse

  • Analog Design Engineer at GET2SPEC, INC.
  • San Diego, California, United States
  • Semiconductors

Education

Rochester Institute of Technology, Master of Science – MS, Electrical Engineering

Public Profile

Background

Experience

  • Analog Design Engineer

    GET2SPEC, INC.

    June 2018 – Present(1 year 4 months)

Education

  • Rochester Institute of Technology

    Master of Science – MS, Electrical Engineering

    2015 – 2017

  • SRM University

    Bachelor of Technology – BTech, Electrical and Electronics Engineering

    2011 – 2015

    Activities and Societies

    International Society of Technology in Education Talent Arena

Projects

  • Multi-Gate Metal Oxide Field Effect Devices

    January 2017 – May 2017

    Wrote a report studying features of multiple-gate FET’s as well as the need to switch from single gate to multiple gate devices, showing how performance of FET’s improves with use of multiple gate devices as the size of devices is reduced to >25 nanometres gate length and focuses on the improvement in threshold voltage of device with the use of double gate FET as compared to single gate FET and carried out necessary simulations using SILVACO: ATHENA and ATLAS tools.

    Team Members (1):
    • Siddhant Cocasse
  • High Voltage Swing Two Stage OTA

    September 2016 – October 2016

    Designed a two-stage operational amplifier (Op-Amp) with very high voltage swing and low power consumption for given set of operating parameters using Cadence Virtuoso and created a layout for the same using Placement and Routing tool on 45-nm process library. Created test benches to study the operating properties of the circuit. It was later used to design a 6-bit flash ADC.

    Team Members (1):
    • Siddhant Cocasse
  • Bandgap Reference Voltage (Brokaw Cell)

    October 2017 – November 2017

    Designed a Bandgap reference voltage with output voltage equal to bandgap of silicon. Created a test bench to study the change in output for several types of resistors available on the Cadence 45nm process library to find the one with lowest temperature coefficient.

    Team Members (1):
    • Siddhant Cocasse
  • Designed 6-bit pipelined Flash ADC using two 3-bit Flash ADC

    Designed a 6-bit pipelined flash ADC using two 3-bit flash ADC containing seven 3-stage CMOS comparators and combination of 2:1 MUX used as encoder to convert the 7-bit output from the comparators. Test benches to test the performances like gain hysteresis, Differential non-linearity. A layout at each stage of design was also created and later combined to create the final 6-bit ADC using Cadence virtuoso tools

    Team Members (1):
    • Siddhant Cocasse
  • Phase Locked Loop

    June 2018 – July 2018

    Created Testbenches and layouts for Phase locked loop system including phase detector, charge pump, VCO to test various features of the EDA tool being developed like LVS, matching, DRC, running verilog scripts.

    Team Members (1):
    • Siddhant Cocasse
  • IP migration to different process technology

    July 2018

    Helped migrate existing IP’s like band-gap voltage references, clock generators, current generators from 40nm process to 22nm, 16nm and 14nm and create test-benches to meet the given specs.

    Team Members (1):
    • Siddhant Cocasse
  • Model creation and editing

    July 2018

    Studied BSIM4, BSIM-CMG, BSIM-IMG models to help create model for XYCE simulator using BSIM4 model .

    Team Members (1):
    • Siddhant Cocasse
  • Banking environment workflow automation

    September 2015 – October 2015

    Developed an application using QNX environment simulating a banking environment using ring buffer and implemented a single queue with queuing to multi-threaded server. The project simulated three bank tellers with a real-time queue using a ring buffer adding and removing customers with three different tasks while tellers taking breaks, all executed using four threads and semaphores.

    Team Members (1):
    • Siddhant Cocasse
  • Servo Motors Automation

    October 2015 – November 2015

    Created an application to simultaneously control a pair of servo motors using the “QNX Purple Box” and Freescale 68HCS12 board, exhibiting multitasking characteristics using communication between the two processors. A square wave was generated using Freescale board with PWM depending on users input on QNX Purple Box to control the rotation of the motors.

    Team Members (1):
    • Siddhant Cocasse
  • Car Parking Assist using Ultrasonic Sensor

    September 2015

    Created a car parking assist application using QNX Neutrino and an Ultrasonic sensor to calculate the distance between the sensor and an obstacle using a multi-threaded system.

    Team Members (1):
    • Siddhant Cocasse
  • Charge Sharing DAC

    September 2018 – November 2018

    Developed Layout for 12 bit charge sharing DAC in TSMC 16nm FINFET process technology and provided Testbenches for post layout verification including Em and RC extraction.

    Team Members (1):
    • Siddhant Cocasse
  • LDO

    April 2019

    working on creating layout for LDO in 14nm FINFET technology

    Team Members (1):
    • Siddhant Cocasse
  • Bandgap and current biasing circuit

    August 2019 – September 2019

    Created layout and testbenches for a bandgap and current biasing circuit for a SERDES Design in gf14 and t16 process technology to provide 16uA of current over -40 to 125 degrees Celsius temperature range

    Team Members (1):
    • Siddhant Cocasse
  • High Speed PLL

    June 2019

    Providing layouts for high speed(16GHz) and high power PLL circuit. Came up with techniques to handle high currents to satisfy Electromigration in TSMC 16nm process technology and reduce parasitic capacitance to maintain performance

    Team Members (1):
    • Siddhant Cocasse

Skills & Expertise

  • Verilog
  • Embedded C
  • Analog Circuit Design
  • Semiconductor Device
  • Embedded Systems
  • Embedded C++
  • Cadence Virtuoso Layout Editor
  • Cadence Virtuoso
  • C++
  • Cadence Spectre

Courses

GET2SPEC, INC.

  • Analog IC Design

Rochester Institute of Technology

  • MEM’s Evaluation
  • Analog IC Design
  • Real Time operating systems
  • Advanced Field Effect Devices
  • Semiconductor Process Integration
  • Micro Fabrication
  • Advanced Carrier Injection Devices