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Pavan Vyas

2ndPremium Subscriber

Previous positions

  • Research Assistant at Stony Brook University


Stony Brook University, Master’s Degree, Electrical Engineering




Software Engineer with focus on software security, embedded systems


  • Security Software Engineer


    February 2017 – Present(2 years 8 months)San Diego, California

    I am working on developing software for QSEE- Qualcomm Secure Execution Environment based on ARM trustzone implementation, secure boot loader development establishing root of trust chain model, and enabling secure debug capabilities on secure boot enabled device. Involved in full life cycle of the latest chipset starting from pre-silicon development to silicon on dock bring up to customer release.

  • Research Assistant

    Stony Brook University

    June 2016 – December 2016(6 months)

    Hardware Generation from Signal Temporal Logic. Using Lexical Analyzer FLEX and BISON to form a parser tree in C++ that generates synthesisable Verilog codes of Hardware Monitors from STL specification to be loaded on FPGA for runtime monitoring of real time digital/mixed signal systems.


  • Stony Brook University

    Master’s Degree, Electrical Engineering

    2015 – 2016

  • L.D College of Engineering – Ahmedabad

    Bachelor’s Degree, Electronics and Communications Engineering

    2011 – 2015

    Actively participated in various organizations such as IEEE student branch, Vox Populi – college magazine club and also won gold medal for my college in sport badminton.


  • English

  • Hindi

  • Gujarati


  • Design of Dual Issue Pipelined Multimedia Processor.

    January 2016 – May 2016

    Designing Sony’s Cell Synergistic Processor Unit (SPU) microarchitecture with improved branch capabilities using System Verilog HDL. Forwarding Scheme implemented to support pipelining. Hazard unit to handle Data Hazardd, Control Hazard and Structural Hazard. Dual issue pipeline supports over 54 instructions. Parser in C language for parsing Assembly language.

    Team Members (2):
    • Pavan Vyas,
    • Rohan Sikka
  • Synthesizable Asynchronous FIFO design in Verilog

    October 2016

    Designed and implemented a parameterized Asynchronous FIFO using Verilog HDL having Gray Code counters. It supported dual port memory, comparators for empty and full condition and clock synchronizer module. Verification test bench was implemented in System Verilog to test the functionality. Simulation is performed in ModelSim.

    Team Members (1):
    • Pavan Vyas
  • Hardware Generation Tool for Matrix vector Multiplier

    December 2015

    Language used : System Verilog and C The software takes in inputs such as Matrix Size, Data Precision, amount of Parallelism/Pipelining and generate 1. RTL design in System Verilog. 2. Random generator testbench for verification (in System Verilog). Design structured using Control Logic and Data Path (FSM). Timing analysis done in ModelSim. Synopsis Design Compiler used for synthesis.

    Team Members (1):
    • Pavan Vyas
  • 6T SRAM Cell Design

    January 2016

    Designed 6T Memory Cell in Cadence Virtuoso. Simulated the design with minimum possible transistor sizes while maintaining certain pull up ratios of the transistors.

    Team Members (1):
    • Pavan Vyas
  • Design of a 32 bit Full Custom Block for an Arithmetic Core using Cadence Virtuoso

    December 2015

    4 bit pipelined Carry Select Adder was used as a building block. Goal was to Maximize Clock frequency, reduce power consumption and layout area

    Team Members (1):
    • Pavan Vyas
  • Survey on STT MRAM

    April 2016

    Conducted and presented a survey on the ongoing research topic towards Magneto-resistive Random Access Memory as main memory. Studied its functioning and future scope over existing memory structures.

    Team Members (1):
    • Pavan Vyas
  • Matrix Multiplication Hardware

    December 2015

    Languages used : SystemVerilog & C. Multiply and Accumulate (MAC) unit designed, combining the ideas of datapath and control logic. Testbench written in C. Synopsis Design Compiler used for Synthesis.

    Team Members (1):
    • Pavan Vyas
  • Clock Distribution Network.

    April 2016

    Devised a schematic of clock distribution network with strict constraints on clock frequency, clock skew and clock slew in Cadence Virtuoso.

    Team Members (1):
    • Pavan Vyas
  • Design and Verification of SPI

    June 2015

    Communication Controller SPI implemented in Verilog. Data width : 8 bits SPI Master : coded in FSM Clock Frequency : 127 Mhz. Timing Analysis : ModelSim Synthesis : Synopsis Design Compiler.

    Team Members (1):
    • Pavan Vyas
  • Obstacle Avoidance/ Path Finder Robot

    May 2014

    Platform : Arduino Mega The project aimed at developing an Autonomous obstacle avoidance robot built in with ultrasonic and touch sensors. The design was further upgraded to make an autonomous Vacuum Cleaner Robot that vacuums the entire room and mops the floor without human intervention. Some key points of the Algorithm : 1. Critical point detection. 2. Determining the Shortest path to cover that critical point. 3. Adjacent graph theory.

    Team Members (1):
    • Pavan Vyas

Skills & Expertise

  • ASIC
  • Digital Circuit Design
  • Verilog
  • Python
  • Microsoft Office
  • Cadence Virtuoso
  • Integrated Circuit Design
  • RTL Verification
  • C
  • SystemVerilog
  • C++
  • Synopsys tools
  • Microsoft Word
  • Bash
  • ModelSim
  • Logic Design
  • Cadence Spectre


Stony Brook University

  • Nanoscale Integrated Circuit Design(ESE 585)
  • Advanced Digital System Design and Generation(ESE 507)
  • Advanced vlsi Systems Design(ESE 555)
  • Integrated Circuits(ESE 516)
  • Solid State Electronics(ESE 511)
  • Computer Architecture(ESE 545)

L.D College of Engineering – Ahmedabad

  • Object Oriented Programming
  • Digital Logic Design
  • Microcontroller and Interfacing
  • Microprocessor and Interfacing
  • Vlsi technology and Design
  • Advanced Electronics

Honors & Awards

  • University Badminton Champion

    Gujarat Technological University

    February 2014

    Winner of the University Badminton Championship. Also led the University badminton team at All India University Badminton Championship.

  • Educational Scholarship

    State Government

    August 2011

    Bearer of the Central Level Educational Scholarship Scheme for my excellence in high school. Secured 99.59 percentile in high school.

  • Sports Scholarship

    State Government

    August 2011

    Bearer of Sports Scholarship Scheme for my all round excellence in sport and academics. Represented Gujarat State thrice at National Level in Badminton


  • IEEE student branch

    Student member

    February 2012 – March 2015

Volunteer Experience & Causes

Causes Pavan cares about:

  • Animal Welfare
  • Education
  • Environment
  • Health
  • Poverty Alleviation
  • Science and Technology
  • Social Services